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PRELIMINARY
CY7C1012DV33
12-Mbit (512K X 24) Static RAM
Features
* High speed -- tAA = 8 ns * Low active power -- ICC = 185 mA @ 8 ns * Low CMOS standby power -- ISB2 = 25 mA * Operating voltages of 3.3 0.3V * 2.0V data retention * Automatic power-down when deselected * TTL-compatible inputs and outputs * Available in Lead Pb-Free Standard 119-ball PBGA power-down feature that significantly consumption when deselected. reduces power
Writing the data bytes into the SRAM is accomplished when the chip select controlling that byte is LOW and the write enable input (WE) input is LOW. Data on the respective input/output (I/O) pins is then written into the location specified on the address pins (A0-A18). Asserting all of the chip selects LOW and write enable LOW will write all 24 bits of data into the SRAM. Output enable (OE) is ignored while in WRITE mode. Data bytes can also be individually read from the device. Reading a byte is accomplished when the chip select controlling that byte is LOW and write enable (WE) HIGH while output enable (OE) remains LOW. Under these conditions, the contents of the memory location specified on the address pins will appear on the specified data input/output (I/O) pins. Asserting all the chip selects LOW will read all 24 bits of data from the SRAM. The 24 I/O pins (I/O0-I/O23) are placed in a high-impedance state when all the chip selects are HIGH or when the output enable (OE) is HIGH during a READ mode. For further details, refer to the truth table of this data sheet.
Functional Description
The CY7C1012DV33 is a high-performance CMOS static RAM organized as 512K words by 24 bits. Each data byte is separately controlled by the individual chip selects (CE1, CE2, CE3). CE1 controls the data on the I/O0-I/O7, while CE2 controls the data on I/O8-I/O15, and CE3 controls the data on the data pins I/O16-I/O23. This device has an automatic
Functional Block Diagram
INPUT BUFFER
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
ROW DECODER
512K x 24 ARRAY
SENSE AMPS
I/O0-I/O7 I/O8-I/O15 I/O16-I/O23
COLUMN DECODER
CONTROL LOGIC
CE1, CE2, CE3 WE OE
Selection Guide
-8 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 8 185 25 Unit ns mA mA
Cypress Semiconductor Corporation Document #: 38-05610 Rev. *B
A10 A11 A 12 A 13 A 14 A15 A16 A17 A18
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised September 4, 2006
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PRELIMINARY
Pin Configurations[1]
119 PBGA
Top View
CY7C1012DV33
1 A B C D E F G H J K L M N P R T U NC NC I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 NC I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC NC
2 A A NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A
3 A A CE2 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NC A A
4 A CE1 NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC WE OE
5 A A CE3 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NC A A
6 A A NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A
7 NC NC I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 NC I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 NC NC
Note: 1. NC pins are not connected on the die
Document #: 38-05610 Rev. *B
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PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC Relative to GND[2] .... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2] ....................................-0.5V to VCC + 0.5V DC Input Voltage[2] .................................-0.5V to VCC + 0.5V
CY7C1012DV33
Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............. ...............................>2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 3.3V 0.3V
DC Electrical Characteristics Over the Operating Range
-8 Parameter VOH VOL VIH VIL[2] IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-down Current --TTL Inputs Automatic CE Power-down Current --CMOS Inputs GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC IOUT = 0 mA CMOS levels Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Test Conditions VCC = Min., IOL = 8.0 mA 2.0 -0.3 -1 -1
[7]
Min. 2.4
Max. 0.4 VCC + 0.3 0.8 +1 +1 185 30 25
Unit V V V V A A mA mA mA
VCC = Min., IOH = -4.0 mA
Capacitance[3]
Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 8 10 Unit pF pF
Thermal Resistance[3]
Parameter JA JC Description Test Conditions All - Packages TBD TBD Unit C/W C/W Thermal Resistance (Junction to Ambient) Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board Thermal Resistance (Junction to Case)
AC Test Loads and Waveforms[4]
50 OUTPUT Z0 = 50 VTH = 1.5V 30 pF* * Capacitive Load consists of all components of the test environment. ALL INPUT PULSES 3.0V 90% GND Rise time > 1 V/ns 10% 90% 10% Fall time: > 1 V/ns OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 351 3.3V R1 317
(a)
(b)
(c)
Notes: 2. VIL (min.) = -2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. 4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). 100 s (tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
Document #: 38-05610 Rev. *B
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PRELIMINARY
AC Switching Characteristics Over the Operating Range
Parameter Read Cycle tpower[6] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW
[10, 11] [5]
CY7C1012DV33
-8
Description VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE active LOW to Data Valid[7] OE LOW to Data Valid OE LOW to Low-Z
[8] [8]
Min. 100 8
Max.
Unit s ns
8 3 8 5 1 5 3 5 0 8 5 1 5 8 End[7] 6 6 0 0 6 5 0 3 5 6
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
OE HIGH to High-Z
CE active LOW to Low-Z[7, 8] CE deselect HIGH to CE active LOW to CE deselect HIGH to High-Z[7, 8] Power-down[7, 9] Power-up[7, 9]
Byte Enable to Data Valid Byte Enable to Low-Z[8] Byte Disable to High-Z[8]
Write Cycle Time CE active LOW to Write Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to Low-Z[8] WE LOW to High-Z[8] Byte Enable to End of Write
Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output loading as shown in part a) of the AC test loads, unless specified otherwise. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed. 7. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 or CE2 or CE3 LOW. When deselect HIGH, CE indicates the CE1 and CE2 and CE3 HIGH 8. tHZOE, tHZCE, tHZWE, tHZBE, and tLZOE, tLZCE, tLZWE, tLZBE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 9. These parameters are guaranteed by design and are not tested. 10. The internal write time of the memory is defined by the overlap of CE1 or CE2 or CE3 LOW and WE LOW. The chip enables must be active and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05610 Rev. *B
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PRELIMINARY
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR tCDR[3] tR[12] Description VCC for Data Retention Data Retention Current VCC = 2V , CE1 > VCC - 0.2V, CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V 0 tRC Conditions Min. 2
CY7C1012DV33
Typ. Max. 25 Unit V mA
Chip Deselect to Data Retention Time Operation Recovery Time
ns ns
Data Retention Waveform
DATA RETENTION MODE VCC 3V tCDR CE VDR > 2V 3V tR
Switching Waveforms
Read Cycle No. 1[13, 14]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)[7, 14, 15]
ADDRESS tRC CE tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE
Notes: 12. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05610 Rev. *B
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PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[7, 16, 17]
tWC ADDRESS tSCE CE tSA tAW tPWE WE tSD DATA I/O DATA VALID tHD tSCE tHA
CY7C1012DV33
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[16, 17]
tWC ADDRESS tSCE CE
tAW tSA WE tPWE
tHA
OE tSD DATA I/O NOTE 18 tHZOE DATAIN VALID tHD
Write Cycle No. 3 (WE Controlled, OE LOW)[7, 17]
tWC ADDRESS tSCE CE tAW tSA WE tSD DATA I/O NOTE 18 tHZWE
Notes: 16. Data I/O is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 18. During this period the I/Os are in the output state and input signals should not be applied.
tHA tPWE
tHD
DATA VALID tLZWE
Document #: 38-05610 Rev. *B
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PRELIMINARY
Truth Table
CE1 H L H H L L H H L L CE2 H H L H L H L H L L CE3 H H H L L H H L L L OE X L L L L X X X X H WE X H H H H L L L L H I/O0-I/O7 High-Z Data Out High-Z High-Z Full Data Out Data In High-Z High-Z Full Data In High-Z I/O8-I/O15 High-Z High-Z Data Out High-Z Full Data Out High-Z Data In High-Z Full Data In High-Z I/O16-I/O23 High-Z High-Z High-Z Data Out Full Data Out High-Z High-Z Data In Full Data In High-Z Read Read Read Read Write Write Write Write
CY7C1012DV33
Mode Power-down
Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Selected, Active (ICC) Outputs Disabled
Ordering Information
Speed (ns) 8 Ordering Code CY7C1012DV33-8BGXC Package Name 51-85115 Package Type Operating Range
119-ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-free) Commercial
Document #: 38-05610 Rev. *B
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PRELIMINARY
Package Diagram
119-ball PBGA (14 x 22 x 2.4 mm) (51-85115)
CY7C1012DV33
51-85115-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05610 Rev. *B
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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PRELIMINARY
Document History Page
Document Title: CY7C1012DV33 12-Mbit (512K X 24) Static RAM Document Number: 38-05610 REV. ** *A ECN NO. 250650 469517 Issue Date See ECN See ECN Orig. of Change SYT NXR New Data Sheet
CY7C1012DV33
Description of Change Converted from Advance Information to Preliminary Corrected typo in the Document Title Removed -10 and -12 speed bins from product offering Changed J7 ball of BGA from DNU to NC Removed Industrial Operating range from product offering Included the Maximum ratings for Static Discharge Voltage and Latch Up Current on page #3 Changed ICC(Max) from 220 mA to 150 mA Changed ISB1(Max) from 70 mA to 30 mA Changed ISB2(Max) from 40 mA to 25 mA Specified the Overshoot spec in footnote # 1 Updated the Truth Table Updated the ordering Information table Added note# 1 for NC pins Changed ICC spec from 150 mA to 185 mA Updated Test Condition for ICC in DC Electrical Characteristics table Added note for tACE, tLZCE, tHZCE, tPU, tPD, tSCE in AC Switching Characteristics Table on page# 4
*B
499604
See ECN
NXR
Document #: 38-05610 Rev. *B
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